With the development of conventional manufacturing technologies of integrated circuit and trend of minimizing semiconductor device size, heat dissipation of devices plays an important role in improvement of semiconductor device performance. Making a minimum size package that contains semiconductor chips with maximum size is a challenge for the semiconductor industry. In a power semiconductor device, for example the DC-DC converter, high side (HS) and low side (LS) transistors are usually packaged in the same package.
Usually, in a manufacturing process of semiconductor, especially in the packaging process, various heat dissipation modes are designed depending on the device's size to improve the device performance. FIG. 1 and FIG. 2A-2E are schematic diagrams illustrating a stacked power semiconductor device in prior art. Specifically, FIG. 1 is a top view of a semiconductor package 100 and FIGS. 2A-2C are cross sectional views of package 100 in FIG. 1 along A-A line, B-B line, and C-C line respectively. As shown in FIG. 1, a first and second top bases 101a and 101b of a top lead frame are electrically connected to first and second electrodes at the front side of a first semiconductor chip 111. The first and second top bases 101a and 101b are used for heat dissipation and also used to connect the electrodes of the first semiconductor chip 111 to the outside electrical components. First and second bases 102a and 102b of a middle lead frame in FIGS. 2B-2C are located under the first semiconductor chip 111 with the second base 102a electrically connected to a portion of an electrode at the back side of the first semiconductor chip 111. First and second bases 102a and 102b are also electrically connected to a first and second electrodes at the front side of a second semiconductor chip 112, while an electrode at the back side of the second semiconductor chip 112 is connected to a bottom lead frame 103 that is used to connect the bottom electrode of the second semiconductor chip 112 to outside electrical components and also used for heat dissipation. FIG. 2E is a bottom-view schematic diagram of the package 100 with pins 103a, 103b, 103c and 103d distributed around the bottom lead frame 103 and pin 103a connected to the bottom lead frame 103.
Refer to FIG. 2C, pins 103b and 103d are respectively connected to the first and second base 101a and 101b by the extending parts 103e and 103f extending upward and approximately close to the plane of the base 102a. For the clarity, the welding material that connects the electrode of the first semiconductor chip 111 to the bases 101a, 101b and 102a and connects the electrode of the second semiconductor chip 112 to the bases 102a, 102b and 103a are not presented in the FIGS. 2A-2C.
In addition, the bases 101a and 101b have different heights, i.e., the top portions of the bases 101a and 101b are not in the same plane, as shown in FIG. 2C. Therefore, the second base 101b is plastically covered by a molding compound, while the top surface of the first base 101a is exposed out of the molding compound of the package 100. In FIG. 2B, in order to prevent the second base 102b from contacting the back side of the first semiconductor chip 111, the second base 102b is located below the first base 102a. 
However, the thermal and electrical properties of the power device of the prior art as described above are not optimized, particularly for the vertical semiconductor devices. As such, various embodiments of the present invention are proposed to obtain a semiconductor package with minimum package size and maximum semiconductor chip size.